The paper focused in addressing the auto align defect at in-strip testing of a semiconductor scalable device in a leadframe technology. Pareto diagram and potential risk analysis were completed to identify the top reject contributors and eventually come-up with the robust solutio...
Open access
Research Article10.9734/jerr/2020/v18i117197
The paper focused in addressing the package voids defect of a semiconductor device utilizing an extremely small leadframe technology. Potential risk analysis and pareto diagram were completed to identify the top reject contributors and eventually come-up with the robust solution....
Open access
Research Article10.9734/jerr/2020/v16i417172
The paper focused in addressing the silicon die chippings defect at the wafer sawing process of an extremely small semiconductor package. In-depth potential risk analysis and Pareto diagram were done to identify the top reject contributors and eventually resolve the issue. A comp...
Open access
Research Article10.9734/jerr/2020/v12i317082
With new and continuous semiconductor technology trends, challenges in assembly manufacturing are inevitable. This paper focused on the elimination of assembly defects particularly package chip-out and scratch at the singulation end-of-line (EOL) process of a semiconductor device...
Open access
Research Article10.9734/jerr/2020/v12i317079
New devices and new technologies in semiconductor industry are getting more complex in terms of package layout, direct materials, and process capability. With the package design complexity, several issues are encountered during the development, and in turn affecting the overall...
Open access
Research Article10.9734/jerr/2020/v11i217059