Wirebonding is one of the most challenging assembly manufacturing processes in semiconductor packaging industry. This paper discussed the wirebonding challenge and the solution to mitigate misplaced ball issues and prevent pattern recognition alignment errors. Parameter optimizat...
Open access
Research Article10.9734/jerr/2021/v20i317283
The paper focused on the improvement done in quad-flat no-leads (QFN) leadframe package assembly to address the quantity of rejection of crumpled leadframe during handling at wirebond process station. Overload sensor at the output magazine handler was found out to be defective, h...
Open access
Research Article10.9734/jerr/2020/v19i217226
This paper presents the modification and improvement done on the wire clamp and top plate (WCTP) design to eliminate the bouncing effect of the silicon die that leads to smashed ball reject during the formation of wire. The protrusion of the unit on the vacuum hole produced movem...
Open access
Research Article10.9734/jerr/2020/v17i417195
New design for a certain issue in semiconductor industry is another way to modify the standard configuration into specified limit or to make a possible solution of the problem. This paper presents a new modified design for wirebond top plate with a bias platform structure that w...
Open access
Research Article10.9734/jerr/2019/v9i317021
Wirebonding process is one of the most challenging assembly manufacturing process in semiconductor packaging industry. This paper discussed the wirebonding challenge and the solution to resolve the wire to die shorting on reverse stitch on ball (RSOB) and prevent irregular loopin...
Open access
Research Article10.9734/jerr/2021/v20i1017387
This technical paper presents a study of wirebond selection highlighting the package electrical modeling and simulation done for semiconductor integrated circuit (IC) leadframe package (hereinafter referred to as Device Z) with different wirebond configurations: Gold 2N 1.3 mil,...
Open access
Research Article10.9734/jerr/2019/v7i316970
The integrity of the assembly wirebond process’ 2nd bond poses a big challenge for semiconductor manufacturing of quad-flat no-leads (QFN) devices, particularly on multiple wires on a lead. These devices are vulnerable to induce or obtain broken wire at heel defect. This type of...
Open access
Research Article10.9734/jerr/2021/v20i817363