With the new devices and new technologies in the semiconductor industry are getting more challenging to process because issues are unavoidable especially on thin dies. The paper is focused on the improvement done on a ball grid array (BGA) substrate package assembly to address th...
Open access
Research Article10.9734/jerr/2021/v20i317277
This paper presents the application of an innovative design of wirebond process plate during wirebonding process of thin semiconductor carrier such as the pre-encapsulated leadframe. The implementation of the specialized process plate aims to improve the conventional method of wi...
Open access
Research Article10.9734/jerr/2020/v16i217162
The need of data storage devices and new technologies continues to grow with more robust and stable functioning capability. With that, improvement and utilization never stop for a seamless output. One device that is currently on new product introduction is a quad-flat no-leads (Q...
Open access
Research Article10.9734/jerr/2020/v14i117114
An alternative design of Quad-Flat No-lead (QFN) leadframe capable with three or more arrays of lead is discussed and presented on this paper. The leadframe design is integrated with connecting bars that can be routed and bonded with wires to decrease the wire span and create a m...
Open access
Research Article10.9734/jerr/2020/v11i217056
Breakthroughs and innovations are constantly being developed in electronic packaging industry to address the manufacturing challenges and overcome existing assembly limitations. An augmented design of thin Silicon die is introduced to establish a robust and improved interface adh...
Open access
Research Article10.9734/jerr/2021/v20i817358
The paper focused on the evaluation of quad-flat no-leads (QFN) device in tapeless leadframe technology on different diebonder platforms to achieve an acceptable fillet height performance. The study was narrowed down into two main machines with the objective of attaining a fillet...
Open access
Research Article10.9734/jerr/2021/v20i817353
During new product development of a substrate land grid array (LGA) device, issues were encountered at wirebonding process due to design constraints. This paper is focused on addressing the wire-to-wire short defect during wirebonding process of the first bond. Wirebond process o...
Open access
Research Article10.9734/jerr/2021/v20i417297
The paper focused on the improvement done in chip on lead (COL) leadframe package assembly manufacturing to address the leadframe bouncing effect during die attach process. A new and enhanced process plate is designed with multi-hole configuration to provide a strong vacuum under...
Open access
Research Article10.9734/jerr/2020/v18i317208
The paper focused on the evaluation of quad-flat no-leads single-row (QFN-sr) leadframe package for die shear test performance on different diebond machine platforms. Die shear test determines the adhesion strength on the interface between the silicon die and the die attach glue...
Open access
Research Article10.9734/jerr/2020/v16i317169
The paper focused in addressing wire-related assembly issues due to tight clearances in the semiconductor package design. Package design characterization was done considering the assembly design rules and the advanced rules, resulting to the integration of an interposer in the pa...
Open access
Research Article10.9734/jerr/2020/v11i217054
The paper focused in addressing the auto align defect at in-strip testing of a semiconductor scalable device in a leadframe technology. Pareto diagram and potential risk analysis were completed to identify the top reject contributors and eventually come-up with the robust solutio...
Open access
Research Article10.9734/jerr/2020/v18i117197
With new and continuous semiconductor technology trends, challenges in assembly manufacturing are inevitable. This paper focused on the elimination of assembly defects particularly package chip-out and scratch at the singulation end-of-line (EOL) process of a semiconductor device...
Open access
Research Article10.9734/jerr/2020/v12i317079
Improvement on the process and design is often a reliable way to resolve a problem especially in semiconductor industry. This paper presents a leadframe or semiconductor carrier merged with a stand-off design structure that will maintain a consistent bond line thickness (BLT) cri...
Open access
Research Article10.9734/jerr/2020/v11i117051