Reza Sabbaghi- Nadooshan

A Fast-Lock Low-Jitter DLL with Double Edge Synchronization in 0.18µm CMOS Technology

Saman Mohammadi Mohaghegh & Reza Sabbaghi- Nadooshan · Current Journal of Applied Science and Technology · 2013

Aims: This paper describes a fast-lock, low-power, low-jitter and good duty-cycle correction capability delay locked loop with double edge synchronization which is mainly used in clock alignment process. A clock aligner’s task is to phase-align a chip internal clock with a refere...