Investigation on Die Crack in a Stacked Die Package Using Finite Element Analysis

Abstract

Die crack is one of the problems in stacked die semiconductor packages. As silicon dies become thinner in such packages due to miniaturization requirement, the tendency to have die crack increases. This study presents the investigation done on a die crack issue in a stacked die package using finite element analysis (FEA). The die stress induced during the package assembly processes from die attach to package strip reflow was analyzed and compared with the actual die crack failure in terms of the location of maximum die stress at unit level as well as strip level. Stresses in the die due to coefficient of thermal expansion (CTE) mismatch of the package component materials and mechanical bending of the package in strip format were taken into consideration. Comparison of the die stress with actual die crack pointed to strip bending as the cause of the problem and not CTE mismatch. It was found that the die crack was not due to the thermal processes involved during package assembly. This study showed that analyzing die stress using FEA could help identify the root cause of a die crack problem during the stacked die package assembly and manufacturing as crack occurs at locations of maximum stress. The die crack mechanism can also be understood through FEA simulation and such understanding is very important in coming up with robust solution.