Augmented Sidewall Topology Simulation of Semiconductor Die
Rennier Rodriguez, Frederick Ray Gomez, Edwin Graycochea Jr.
Journal of Engineering Research and Reports · pp. 70–74 · Published 8 May 2021
10.9734/jerr/2021/v20i617329Abstract
The paper presents a modified design for wafer level semiconductor devices, using a CAD (computer-aided design) tool for visualization. The discussion provides a specialized manufacturing flow for the augmented die design through advanced wafer fabrication method and wafer cutting technique. Ultimately, the new package design would result for better visual inspection and interface anchoring between the device and the external board.
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