Edge-Intelligence Framework for Binary Predictive Maintenance Diagnosis in Industrial Manipulator Workstations

Abstract

Modern industrial manipulators operating within human-in-the-loop environments generate highly variable, noise-contaminated telemetry that can reduce the reliability of centralised predictive maintenance models. Cloud-based diagnostic architectures are constrained by communication bandwidth limitations, security vulnerabilities, and non-deterministic transmission latencies. To address these challenges, this paper introduces an autonomous, licence-free edge-intelligence framework designed for real-time in situ kinematic fault diagnosis without external computational or cloud dependencies. The studied architecture couples an event-driven Node-RED data orchestration engine with a synchronised, multi-channel sliding-window preprocessing pipeline. This architecture was empirically validated on an active production floor using multivariable telemetry, comprising motor current, axial vibration, and joint temperature, captured over a continuous 250-second sequence encompassing 50 distinct human-driven manual execution cycles. Through preprocessing via an 80%-overlapping sliding-window protocol (W = 10 s, S = 2 s), the framework generated 116 serialised feature windows, comprising 80 windows for training and 36 windows for independent testing. Raw telemetry was compressed into a low-dimensional feature space that isolates structural degradation markers from human-induced operational transients. Evaluated using a block-stratified 5-fold cross-validation scheme to prevent temporal data leakage, the native edge-compiled binary decision tree achieved classification accuracy and precision of 100% on the independent evaluation blocks. By restricting the classifier split depth, the diagnostic logic compiles directly into standard nested C-style conditional loops. Hardware profiling on a target ARM Cortex-M7 microcontroller demonstrated ultra-low-overhead execution, requiring an inference latency of less than 1.2 microseconds and a memory footprint below 8 KB, leaving 99.2% of the on-chip RAM free for core control loops. This framework provides a verifiable blueprint for low-overhead, high-precision hardware-in-the-loop implementation of binary fault isolation within a localised mechatronic workstation environment.