A Novel Multiplier Using Vedic Mathematics and Booth Encoding

Abstract

In this paper a comparative study of multiplier is done for speed.  The concept used in the proposed algorithm is the combination of “Urdhva Tiryagbhyam” algorithm and Booth encoding for performing multiplication. The “Urdhva Tiryagbhyam” algorithm is an ancient Indian Vedic mathematics, which is used for multiplication to improve the speed and area [1].  The multipliers based on the concept of Booth encoding are compact and have significantly a higher speed when compared to their non encoded counterparts [2]. The approached architecture for a multiplier uses Booth encoder, Vedic Multiplier, along with parallel adders. The coding for the proposed multiplier is carried out using the hardware descriptive language namely VHDL. Subsequently the code is simulated and synthesized using Xilinx ISE 10.1 software. This multiplier is implemented on Spartan 3 FPGA devices XC3S50- 5pq208. The performance metrics for comparing the Booth encoded multiplier and the Vedic multiplier is the speed of operation and the device utilization summary, when both the algorithms are implemented on FPGA. It has been observed that the proposed design has speed improvements as compared to the other multipliers.