Influence of Sampling Period on Harmonics of Three- Phase Space Vector Modulated Inverter

Abstract

The three- phase inverter is driven by a number of semiconductor switches for obtaining three-phase output of nearly sinusoidal fundamental voltage. The purpose of the Space Vector Modulation (SVM) technique is to produce three-phase load voltages of fewer harmonics. It can be reached by selecting an appropriate sampling period for the desired circular locus. This paper endeavors to present the influence of the sampling period on inverter output voltages and their harmonics. Simulation results are presented to assess the inverter performance for different values of sampling periods. The results conclude that an optimum inverter output voltage is achieved when the given circular locus of space vector is sampled at a period equals the half interval between of the two adjacent space vectors.