A Study of Wafer Backgrinding Tape Selection for SOI Wafers

Abstract

The continuous development and trends on thinner semiconductor packages have become the focus in the semiconductor industry. The necessity of thinner packages also demands a thinner vertical structure of the integrated circuit (IC) design. As a major contributor on the vertical structure of the IC package, die or wafer is also essential to go thinner. As the wafer goes thinner, various problems may occur during transport and even the backgrinding process, itself. Wafer warpage is one of the main concerns during the backgrinding process. Wafer warpage varies depending on the wafer backgrinding stress and backgrinding tape (hereinafter referred to as BG tape) tension. Hence, tension between the surface protective tape and the wafer should be considered an important and critical item to consider during BG tape selection. Different silicon wafer technology has been released to cater different functionality on different industry markets. One popular silicon technology is Silicon On Insulator (SOI) technology. SOI wafers have a step type passivation wherein the edge of the wafer is observed to have 30um thinner than its center. The stepping effect also contributes to the 0.5mm wafer warpage prior backgrinding. Evaluating the effect of BG tape selection to eliminate such warpage is discussed on this paper.