Metallized Semiconductor Die for Long Wire Interconnect
Frederick Ray I. Gomez, Rennier S. Rodriguez
Journal of Engineering Research and Reports · pp. 20–24 · Published 24 Jul 2020
10.9734/jerr/2020/v14i417131Abstract
This paper focused on the integration of metallized silicon die in design layout of quad-flat no-leads package (QFN) and ball grid array (BGA) devices. The metallized silicon die is fabricated with a conductive top layer where the junction for wire interconnection is created. The conductive top layer formed an intermetallic connection between the gold or copper wire and aluminum metal on the conductive outer layer to produce electrical continuity in the device circuitry. Incorporating the design on conventional QFN and BGA eliminates long wiring layout in the system that is the primary cause of electrical shorting rejection during integrated circuit assembly and testing. For subsequent works, the design could be applied for packages with similar requirement and/or configuration.
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