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Research Article Open access CC BY 4.0

Challenges and Resolution for Copper Wirebonding on Tapeless Leadframe Chip-on-Lead Technology

Antonio R. Sumagpang Jr, Frederick Ray I. Gomez

Journal of Engineering Research and Reports · pp. 1–13 · Published 24 Dec 2018

10.9734/jerr/2018/v3i216869

Abstract

This technical paper discusses a methodological and systematic way of resolving key challenges during introduction of Chip-On-Lead package specifically wirebonding issues that leads to production dilemma during production ramp-up of products using copper wire in tapeless leadframe. The project was intended to determine the “Red-X” or the major cause of yield detractors that may lead to quality issue during wirebonding process. Problem solving tools were showcased in this paper such as Data Analysis, Cause and Effect, Design-of–Experiment (DOE) and mechanical dimensional analysis which provided substantial impact in determining the real root-cause of the problem. Step-by-step elimination of variables was achieved with the use of statistical engineering tools. Outcome of the project eliminated the occurrence of Non-Stick-On-Pad (NSOP) during wirebonding process without cost involved and just optimizing the available in-house resources.  The improvements also enhanced the quality of the product after final test which on the other hand lower the risk of having potential customer complaint in the future.

Chip-on-lead tapeless leadframe copper wirebonding non-stick-on-pad wirebond design-of-experiment.

Cited by 4

Packaging Materials in High-Performance Computing Applications

M. Pulugurtha, Himani Sharma, R. Pucha · Journal of the Indian Institute of Science · 2022

Tool Setup Improvement for Package Scratch Mitigation at End-of-Line Process

A. Sumagpang, F. Gomez, R. Rodriguez · Journal of Engineering Research and Reports · 2020

Specialized Singulation Punch Design for Package Chip-out Elimination

A. Sumagpang, F. Gomez · Journal of Engineering Research and Reports · 2019

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